400MHz Digital Phase Locked Loop

A project for ECE 547 "VLSI Design" - Fall Semester 2003
Department of Electrical and Computer Engineering
University of Maine

Designed by: Devon Fernandez and Sanjeev Manandhar

This chip contains two Digital Phase Locked Loops. One has an operating frequency of 400MHz generated by a vco based on differential logic, a fixed frequency divider of 64, and an xor phase detector. The other has an operating frequency of 25MHz, a programmable frequency divider, and a phase frequency detector.

The project report contains a description of the project and details of the design and layout. A poster depicting our project layout is also available.